Receiver complexity and its resultant circuit bandwidth limitation is one of the main impediments for realizing power and area-efficient high data rate input-output (IO) links. Traditional Decision Feedback Equalizers (DFEs) are not feasible for removing Inter-Symbol-Interference (ISI) at high data rates in receivers of I/O links because traditional DFEs are limited by propagation delay of a closed loop having at least a summer (or adder), sampler(s), delay unit(s), and weight multiplier(s). For ultra-high data rates of 60 Giga bits per second (Gb/s) and more, one technique to improve the data rate and channel loss tolerance of IO transceivers is a DFE with tap speculation (or look-ahead). However, the exponential power and area cost of DFE tap speculation makes it unattractive for links that target power and area efficiency.